In a computer system, a piece of data which is to be transferred from a processor to some form of memory may be referred to as a "store." A "store" (as the term is used herein) may generally include a piece of data or a block of data, address information, and an instruction to transfer the data in memory. In many situations stores are transferred, or "committed," to various caches, which may be included within the processor or otherwise associated with the processor. Certain stores, however, are not amenable to cache storage. Instead, these "uncacheable stores" ("UC stores") must be committed to system memory, such as dynamic random access memory ("DRAM"), other similar memory, or, if suitable, a more permanent storage medium such as a hard drive.
In known processors and systems, UC stores are committed in the form received. That is, stores are committed to memory in the form originally sent, or "executed," by the processor (i.e., in "programatic" order). Because of varying sizes of these stores, however, direct commission to system memory fails to take advantage of the full bandwidth of the bus between the processor and memory. As a result, backups may occur between the processor and memory.
Based on the foregoing, there is a need for a device which makes more efficient use of the bandwidth between the processor and memory, thereby minimizing backups and hardware requirements.